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2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Features
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IDT71T016SA
Description
The IDT71T016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71T016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71T016 are LVTTL-compatible and operation is from a single 2.5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71T016 is packaged in a JEDEC standard a 44-pin Plastic SOJ, 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
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64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times -- Commercial: 10/12/15/20ns -- Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 2.5V power supply Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages
Functional Block Diagram
OE Output Enable Buffer
A0 - A15
Address Buffers
Row / Column Decoders
I/O15 Chip Enable Buffer Sense Amps and Write Drivers 8 Low Byte I/O Buffer 8 8 High Byte I/O Buffer 8
CS
I/O8
WE
Write Enable Buffer
64K x 16 Memory Array
16
I/O7
I/O0
BHE Byte Enable Buffers BLE
5326 drw 01
APRIL 2004
1
(c)2004 Integrated Device Technology, Inc. DSC-5326/01
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A
A4 A3 A2 A1 A0 CS I/O0 I/O1 I/O2 I/O3 VDD VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO44-1 SO44-2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
1 BLE I/O8 I/O9 VSS VDD I/O14 I/O15 NC
2 OE BHE I/O10 I/O11 I/O12 I/O13 NC A8
3 A0 A3 A5 NC NC A14 A12 A9
4 A1 A4 A6 A7 NC A15 A13 A10
5 A2 CS I/O1 I/O3 I/O4 I/O5 WE A11
6 NC I/O0 I/O2 VDD VSS I/O6 I/O7 NC
5326 tbl 02a
B C D E F G H
FBGA (BF48-1) Top View Pin Description
A0 - A15 Address Inputs Chip Select Write Enable Output Enable High Byte Enable Low Byte Enable Data Input/Output 2.5V Power Ground
Input Input Input Input Input Input I/O Power Gnd
5326 tbl 01
5326 drw 02
TSOP Top View
CS WE OE BHE BLE I/O0 - I/O15 VDD VSS
Truth Table(1)
CS H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L H L L L H X H BHE X H L L L H L X H I/O0-I/O7 High-Z DATAOUT High-Z DATAOUT DATAIN DATAIN High-Z High-Z High-Z I/O8-I/O15 High-Z High-Z DATAOUT DATAOUT DATAIN High-Z DATAIN High-Z High-Z Function Deselected - Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Outputs Disabled Outputs Disabled
NOTE: 1. H = VIH, L = VIL, X = Don't care.
5326 tbl 02
6.42 2
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VDD VIN, VOUT TBIAS TSTG PT IOUT Rating Supply Voltage Relative to VSS Terminal Voltage Relative to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.3 to +3.6 -0.3 to VDD+0.3 -55 to +125 -55 to +125 1.25 50 Unit V V
o
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C VSS 0V 0V VDD See Below See Below
5326 tbl 04
C C
o
W mA
Recommended DC Operating Conditions
Symbol VDD Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.375 0 1.7 -0.3
(2)
Typ. 2.5 0
____
Max. 2.625 0 VDD+0.3 0.7
(1)
Unit V V V V
5326 tbl 05
5326 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
____
Capacitance
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
NOTES: 1. VIH (max) = VDD + 1.0V a.c. (pulse width less than tCYC/2) for I < 20 mA, once per cycle. 2. VIL (min) = -1.0V a.c. (pulse width less than tCYC/2) for I < 20 mA, once per cycle.
5326 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71T016SA Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VDD = Max., VIN = VSS to VDD VDD = Max., CS = VIH, VOUT = VSS to VDD IOL = 2.0mA, VDD = Min. IOH = 2.0mA, VDD = Min. Min.
___ ___ ___
Max. 5 5 0.7
___
Unit A A V V
5326 tbl 07
1.7
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD - 0.2V)
71T016SA10 Parameter Symbol ICC Dynamic Operating Current CS < VLC, Outputs Open, VDD = Max., f = fMAX(3) Dynamic Standby Power Supply Current CS > VHC, Outputs Open, VDD = Max., f = fMAX(3) Full Standby Power Supply Current (static) CS > VHC, Outputs Open, VDD = Max., f = 0(3) Max. Typ. (4) Com'l 160 90 45 10 Com'l 150 85 40 15 Ind 160
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71T016SA12
71T016SA15 Com'l 130 80 35 15 Ind 130
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71T016SA20 Com'l 120 80 30 15 Ind 120 mA
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Unit
ISB ISB1
45 15
35 15
30 15
mA mA
NOTES: 5326 tbl 8 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High). 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 4. Typical values are measured at 2.5V, 25C and with equal read and write cycles. This parameter is guaranteed by device characterization but is not production tested.
6.42 3
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load 0V to 2.5V 1.5ns (VDD/2) (VDD/2) See Figure 1, 2 and 3
5326 tbl 09
AC Test Loads
+1.25V 50 I/O Z0 = 50
DATA OUT 5pF*
2.5V 320
350
5326 drw 04
30pF
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*Including jig and scope capacitance.
Figure 1. AC Test Load Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7 tAA, tACS (Typical, ns) 5 4 3
* *
*
6
2 1
* * *
*
8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
5326 drw 05
6.42 4
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol READ CYCLE tRC tAA tACS tCLZ(1) tCHZ(1) tOE tOLZ(1) tOHZ(1) tOH tBE tBLZ(1) tBHZ(1) Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select Hig h to Output in High-Z Output Enable Low to Output Valid Output Enable Lo w to Output in Low-Z Output Enable High to Output in High-Z Output Hold from Address Change Byte Enable Low to Output Valid Byte Enable Low to Output in Low-Z Byte Enable Hig h to Output in High-Z 10
____ ____
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71T016SA12 Min. Max. 71T016SA15 Min. Max. 71T016SA20 Min. Max. Unit Max.
71T016SA10(2) Parameter Min.
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12
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____
15
____ ____
____
20
____ ____
____
ns ns ns ns ns ns ns ns ns ns ns ns
10 10
____
12 12
____
15 15
____
20 20
____
4
____
4
____
5
____
5
____
5 5
____
6 6
____
6 7
____
8 8
____
____
____
____
____
0
____
0
____
0
____
0
____
5 -- 5
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6 -- 6
____
6 -- 7
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8 -- 8
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4 -- 0
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4 -- 0
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4 -- 0
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4
____
0
____
5
6
6
8
WRITE CYCLE tWC tAW tCW tBW tAS tWR tWP tDW tDH tOW
(1)
Write Cycle Time Address Valid to End of Write Chip Select Low to End of Write Byte Enable Low to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable Hig h to Output in Low-Z Write Enable Lo w to Output in High-Z
10 7 7 7 0 0 7 5 0 3
____
____
12 8 8 8 0 0 8 6 0 3
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____
15 10 10 10 0 0 10 7 0 3
____
____
20 12 12 12 0 0 12 9 0 3
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____
ns ns ns ns ns ns ns ns ns ns ns
5326 tbl 10
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tWHZ(1)
5
6
6
8
NOTES: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. 00C to +700C temperature range only.
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC ADDRESS tAA tOH D ATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
5326 drw 06
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW.
6.42 5
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC ADDRESS tAA OE tOE CS tCLZ BHE, BLE tBE tBLZ DATAOUT
(3) (2) (3)
tOH
tOHZ
(3)
tOLZ tACS (2)
(3)
tCHZ
(3)
tBHZ (3) DATA OUT VALID
5326 drw 07
NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured 200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC ADDRESS tAW CS tCW BHE , BLE tWR WE tAS
(3) (5)
(2)
tCHZ
(5)
tBW
(5)
tBHZ
tWP
tWHZ DATAOUT PREVIOUS DATA VALID
tOW tDW DATAIN DATAIN VALID tDH
(5)
DATA VALID
5326 drw 08
NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state.
6.42 6
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC ADDRESS tAW CS tAS tBW BHE, BLE tWP WE tWR tCW (2)
DATAOUT tDW DATAIN tDH
DATAIN VALID
5326 drw 09
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
tWC ADDRESS tAW CS tCW tAS BHE, BLE tWP WE tWR
(2)
tBW
DATAOUT tDW DATAIN DATAIN VALID
5326 drw 10
tDH
NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state.
6.42 7
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71T016 Device Type SA Power XX Speed XXX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
Y PH BF
400-mil SOJ (SO44-1) 400-mil TSOP Type II (SO44-2) 7.0 x 7.0 mm FBGA (BF48-1)
10 ** 12 15 20
Speed in nanoseconds
** C o m m e rcia l te m p e ra tu re
ra n g e o n ly.
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6.42 8
IDT71T016SA, 2.5V CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
Rev 0 1 Date 08/23/01 04/16/04 Page p. 1-8 p. 3 Description Created new datasheet Updated datasheet to full release version. Updated overshoot and undershoot specifications and typical DC electrical characteristics.
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